A one-pass test-selection method for maximizing test coverage | Semantic Scholar (2024)

This work proposes a novel black-box test selection method based on a Bayesian network model that effectively reduces test cost by up to 14.7%, compared to a conventional greedy algorithm.

A method which combines a fast correlation-based filter and a weighted naive Bayesian model which can identify the most effective items and make accurate quality predictions is presented which can effectively reduce the test cost without jeopardizing test quality excessively.

A test selection method based on fault tree analysis is proposed for analyzing the reliability of the board and test items and the reliability analysis result is utilized to design a test strategy.

This article proposes a novel black-box test selection method based on Bayesian networks (BNs), which extract the strong relationship among tests and reduces the test cost when prior information is provided from similar products.

A novel self-gating structure designed to use functional data and scan data selectively to eliminate the unnecessary clock toggling of flip-flops is proposed and the average of the stuck-at test pattern increase ratio has been dropped.

Results show that for the same test length, patterns selected on the basis of output deviations are more effective than patterns selected using several other methods.

A linear programming-based optimal test pattern selection method which aims at reducing the overall defect part level (DPL) and achieves higher defect coverage than traditional n-detection method.

This work presents a test selection procedure for creating a physically- aware N-detect test set that satisfies a user-provided constraint on test-set size and shows that it can virtually detect the same number of faults 10 or more times as a traditional 10-detECT test set without increasing the number of tests.

An integer linear programming (ILP) algorithm for optimally minimizing a given test set for any given N is given; in general, the value of N can be separately specified for each fault.

The IP fault model is described and a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools is provided, used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder.

The defect level model uses the behavior-attribution results of the current failing population to guide test-set customization to minimize defect level for a given constraint on test costs, or alternatively, ensure that defect level does not exceed some predetermined threshold.

A test framework that utilizes the continuous stream of failing test data during production testing to track the varying test quality based on evolving defect characteristics and thus dynamically adjust the production test set to deliver a target defect escape level at minimal test cost is presented.

A new model is proposed which learns the effectiveness of fault models from the diagnostic results of defective chips, and predicts defect level using the derived measures of effectiveness and fault coverages of multiple fault models.

A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips based on a model for the distribution of faults on a chip, which implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment.

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