[PDF] Efficient built-in self test of regular logic characterization vehicles | Semantic Scholar (2024)

The state of a novel test chip design methodology that results in a test chip referred to as the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) is described, which is able to achieve single stuck line fault coverage of up to 99.4%.

This paper describes a multiple-defect, two-level diagnosis procedure that leverages these unique properties of the FUB array to significantly improve diagnosis.

This work explores enhancements to the CM- LCV that make delay faults optimally testable, with specific focus on the path delay fault model.

This work describes an enhanced implementation methodology for the Carnegie-Mellon Logic Characterization Vehicle (CM-LCV) that ensures optimal cell-aware diagnosability by design.

This work describes an enhanced implementation methodology for CM-LCV that not only guarantees 100% intra-cell defect testability for all standard cells but also reflects the user-specified design characteristics.

This work develops a flow using available tools that can automatically synthesize a scalable CM-LCV in very little time with standard-cell characteristics that are nearly identical to product designs.

This work proposes a method called IPSA (Integer Programming via Sparse Approximation) to solve this integer programming (IP) problem in an effective and efficient manner and demonstrates that with more than 100× speed up, IPSA achieves a similar or even better solution compared to directly solving the original problem with a commercial IP solver.

Theoretical and simulation studies were performed to demonstrate that the test pattern generation efficiency of the CTSP is comparable to that of a pseudorandom generator, regardless of the functionality of the circuit under test.

Two algorithms are proposed for self-testing of embedded bedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults.

The main advantage of the proposed approach, called C/sup 2/BIST (circular cellular BIST) is that the same CA is used for generation and compaction, thus lowering substantially the area requirements.

A novel Logic Characterization Vehicle (LCV) is presented to investigate the yield and performance impact of process variation on high volume product chips and can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.

The IP fault model is described and a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools is provided, used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder.

An effective BIST architecture for fast multipliers that completely complies with the requirement for testing of such multiplier cores deeply embedded in complex ICs is introduced.

A new pseudorandom BIST scheme for high-speed adders is presented, where an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing.

The authors investigate the testing properties of a class of regular circuits known as trees, which include parity circuits, multiplexers, and decoders and gives conditions for individually testing the arrays within a tree with a constant number of tests.

Property of systems that enable them to be tested with a fixed constant number of tests independent of p, the number of cells in the system are considered, referred to as C-testable.

...

...