Design reflection for optimal test-chip implementation | Semantic Scholar (2024)

A new method is proposed for constructing a CM-LCV that reflects the design characteristics of a product through rewiring either the entire layout or some portion thereof, and results reveal that front-end masks from an actual product can be re-used to create an effective LCV that is both more reflective and inexpensive to fabricate.

A new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed that utilizes a twodimensional array of functional unit blocks (FUBs) that each implement an innovative functionality that is composable within the FUB array.

This work describes a design flow that efficiently incorporates FEOL layout properties into an easily testable and diagnosable logic-based test chip.

The contributions of this dissertation can be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning and improvement on the state-of-the-art commercial diagnosis.

This work describes an enhanced implementation methodology for CM-LCV that not only guarantees 100% intra-cell defect testability for all standard cells but also reflects the user-specified design characteristics.

This work describes an enhanced implementation methodology for the Carnegie-Mellon Logic Characterization Vehicle (CM-LCV) that ensures optimal cell-aware diagnosability by design.

This work describes a new design flow that significantly accelerates the logic test chip design process, and a new method is described to efficiently solve the integer programming problem involved in the design process.

The state of a novel test chip design methodology that results in a test chip referred to as the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) is described, which is able to achieve single stuck line fault coverage of up to 99.4%.

An automated flow to facilitate SCB-ATC layout design in FinFET technology is described, which can be generated in a design rule error-free manner by virtue of keeping FEOL and MEOL unchanged and BEOL slightly modified.

This work describes a design methodology that deploys a random forest classification technique to predict synthesis outcomes for test chip design exploration and demonstrates that the machine learning aided flow speeds up design by 11× with negligible performance degradation.

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A novel Logic Characterization Vehicle (LCV) is presented to investigate the yield and performance impact of process variation on high volume product chips and can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.

This work describes a BIST scheme that achieves 100% input-pattern fault coverage with an 86.9% reduction in test time for a reference design and all of these properties are achieved with a minimal hardware overhead.

This work reports, for the first time, an addressable array test chip that is capable of full transistor characterization including measuring transistor off current including leakage current measurement.

This paper claims that a far superior result can be achieved by moving the design-to-manufacturing interface from design rules to a higher level of abstraction based on a defined set of pre-characterized layout templates and demonstrates how this methodology can simplify optical proximity correction and lithography processes for sub-32 nm technology nodes.

A novel large-scale addressable test chip development procedure that is fully integrated and able to reduce layout time to 10% and eliminate much of the potential for human error is presented.

The goal of this benchmarking effort is to test new DFT techniques on real designs, using the DAT test generation system and two sequential test generators developed at the University of Iowa.

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